Static timing analysis (STA) is a common method of computing the expected timing of a digital circuit to identify problem areas of an integrated circuit during the design phase and in advance of actual fabrication. The timing of the integrated circuit is simulated to determine if it meets the timing constraints and, therefore, is likely to operate properly if fabricated in accordance with the tested design.
Deterministic STA (DSTA) propagates timing quantities, such as arrival times, required arrival times, and slews, along with any other timing related quantities (guard times, adjusts, asserts, etc.), as single valued deterministic data. DSTA only covers a single corner of a space of process variations with each individual timing run. A corner is a set of input values for parameters that may include temperature of the circuit, input voltage, and various manufacturing parameters of an integrated circuit. In order to evaluate the impact that a given parameter will have on timing, multiple DSTA timing runs must be executed with parameters that affect timing set at several maximum and minimum corners, such as high and low temperature, high and low voltages, and various processing conditions. For example, DSTA timing runs may compare a corner characterized by a combination of high input voltage, a high operating temperature, and the worst manufacturing parameters with a corner characterized by a combination of a low input voltage, a low operating temperature, and the best manufacturing parameters. As a check of the performance of the integrated circuit design, many or all of the corners may be run and the integrated circuit design adjusted until all of the corners pass the timing tests. These results reflect the extreme performance bounds of the integrated circuit and may require numerous timing runs to fully explore the space of process variations. Even then, the results may be overly pessimistic and misleading for optimization tools.
Statistical static timing analysis (SSTA) propagates timing quantities as statistical distributions instead of as single valued deterministic data. In contrast to the DSTA approach that only predicts a single corner of the space of process variations with each timing run, a single timing run using SSTA predicts the performance of the integrated circuit over the entire space of process variations. Consequently, in order to close timing, a single SSTA timing run may replace multiple DSTA timing runs. For example, assuming N parameters (i.e., sources of variation) and two corners per parameter, then 2N corners would have to be analyzed by individual DSTA timing runs to match the effectiveness of a single SSTA run. Hence, SSTA is far more computationally efficient than DSTA. A test run that passes in a single process corner under a DSTA run may actually fail in one or more other performance-limiting corners in the process space, which SSTA would reveal. SSTA methods can, therefore, reduce the exaggerated pessimism inherent in DSTA.
SSTA operates on a timing graph comprised of nodes, which represent points at which signal transitions can occur, and edges that connect incident nodes. Timing values are computed for the timing graph at each node based upon arrival times (ATs), which define the time (or the time distribution) at which a given signal arrives at a timing point, and required arrival times (RATs), which defines the time (or the time distribution) at which the signal is required to get to the timing point, in order to meet the timing requirements. These ATs and RATs are used to compute timing metrics in the form of slacks at nodes (RAT minus AT for late mode and AT minus RAT for early mode). A negative value for either a late mode slack or an early mode slack indicates a timing constraint violation.
Typically, slack data is only collected for timing qualification at a subset of all of the timing graph nodes, sometimes referred to as test points, or endpoints. These endpoints are frequently defined as those nodes that are either primary outputs of the circuit, or those that control data propagation (e.g. the input to storage elements such as latches). There frequently are multiple slacks incident at these nodes, due to both the backward propagated RAT data from upstream nodes, and also due to any timing tests that may be present on those nodes (e.g. setup or hold tests). These slacks may be called edge slacks, as they arise from the timing and test segments that form the graph edges incident on the node of interest. The final slack value for that node is defined as the minimum of all edge slacks, as this is the limiting slack that can cause timing failure.
In deterministic timing analysis, a ‘traditional’ deterministic minimum operation is used, where the smallest of all the incident edge slacks is used to define the nodal slack value. For this reason, an individual edge slack can never be worse than the node slack, and the node slacks always capture the worst timing constraint violations.
In block-based SSTA, statistical minimum and maximum operations used to calculate a node slack for the propagated statistical distributions. As the input data to these operations are functions (statistical distributions), the output of a statistical minimum or maximum operation is also a function. These propagated distributions will typically overlap such that each one will produce a minimum (or maximum) some percentage of the time over numerous samples. Therefore the output function is defined as a linear combination of all of the inputs, with each input weighted by the probability that it will produce either the minimum or the maximum result. Therefore, failing results in a timing report cannot be easily correlated with the actual failing test that produced the fail, which increases the difficulty to trace failing tests as required to resolve timing issues.
Moreover, in block-based SSTA reporting of the slack distribution, an edge slack for a propagated distribution can be worse than the slacks of the nodes connected by the edge because of the statistical maximum and minimum operations performed on the propagated distributions. Problems arise because the timing correctness of a circuit design is often determined by ensuring that all edge slacks are non-negative or, more generally, are greater than some user-specified threshold. Because slacks of the nodes connected by an edge may be higher than the slack of the edge, this leads to a situation in which a timing constraint violation is reported on an edge. However, the slacks of the nodes connected by the edge, which the designers and optimization tools generally use, forming the sink slack do not indicate a timing constraint violation. Therefore, designers and optimization tools may be confused or mislead because of the slacks of the edges are not considered.
Accordingly, there is a need for an improved method for practical worst test definition and debug during block-based SSTA that overcomes these and other deficiencies of conventional block-based SSTA.